Hardware Design & Digital Logic
What it does: Blinks an LED at 1Hz (once per second) by diciding down the FPGA's 100MHz clock to a human visible frequency.
Design Logic: The FPGA's 100MHz clock is too fast for visible LED blinking (100 million cycles/second). Thsi design implements a clock divider using a 26-bit counter that increments on every clock cycle. When the counter reaches 50 million, it resets and toggles the output. Since toggling happens twice per second (at 50M and 100M), the LED blinks at 1 Hz. The 26-bit width was chosed as the
minimum size needed to count to 50 million without wasting FPGA resources.
Results: Successfully creates a 1Hz Square wave output.Runs at 100MHz on Basys3 board. Uses minimal resources. This frequency divider pattern is fundamental to many FPGA designs requiring human visible timing.
A 32-bit RISC-V processor core implementing the RV32I instruction set with a 5-stage pipeline. Features include hazard detection, forwarding, and branch prediction.
Custom 8-bit CPU with 16 instructions, 256 bytes of RAM, and simple I/O. Includes assembler and example programs demonstrating basic computational tasks.
Hardware implementation of a 1024-point FFT using Cooley-Tukey algorithm. Optimized for throughput with pipelined butterfly units and on-chip memory.
Configurable FIR filter with adjustable tap count and coefficients. Implemented using systolic array architecture for high-speed audio processing applications.
Complete VGA controller with sprite engine, double buffering, and custom graphics primitives. Supports 640x480 resolution at 60Hz refresh rate.
